View AK5720VT_8218961.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 1 - 1. g eneral description the ak 5720 is a low voltage 24 - bit a/d converter for digital audio systems. the ak5720 includes an input gain amplifier, making it suitable for microphone applica tions . the analog signal input of the ak5720 is single - ended, eli minating the need for external filters. the ak5720 is housed in a space - saving 16 - pin tssop package. 2. f eatures 1. resolution: 24bits 2. recording functions ? gain amplifier (0db / +15db) ? digital hpf for dc - offset cancellation (fc=1.0hz@fs=48khz) 3. adc characteri stics ? single - ended input ? input level: 1.8vpp@va=3.0v (= 0.6 va), 3.0vpp@va=5.0v (=0.6 va) ? s/(n+d): 94 db ? dr, s/n: 102 db 4. master clock: 256fs/384fs/512fs /768fs 5. sampling frequency : 8khz ? s compliment ? 24 - bit m sb justified, i 2 s and tdm 7. power supply ? va , vd : 2.7 ? 5.5v (typ. 3 v , 5v ) 8. power supply current: 6.1 ma (va - vd=5.0v,fs=48khz) 9. operating temperature: ta = - 40 ? 10 5 ? c 10. package: 16 - pin tssop 96khz 24 - bit ? ? adc ak5 720 lin vcom va vss mclk sdto b ic k lrck vd clock divider pdn rin dif/tdmi g sel adc hpf iiis/tdm out fsel cks rego regu l ator
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 2 - 3. table of contents 1. general description ................................ ................................ ................................ ................................ .... 1 2. features ................................ ................................ ................................ ................................ ....................... 1 3. table of contents ................................ ................................ ................................ ................................ ........ 2 4. pin configurations and functions ................................ ................................ ................................ .............. 3 ordering guide ................................ ................................ ................................ ................................ .......... 3 pin layout ................................ ................................ ................................ ................................ ................. 3 functions ................................ ................................ ................................ ................................ ................... 4 handling of unused pin ................................ ................................ ................................ ............................ 4 5. a bsolute maximum ratings ................................ ................................ ................................ ....................... 5 6. recommended operating conditions ................................ ................................ ................................ ......... 5 7. analog characteristics (va=vd=5.0v) ................................ ................................ ................................ .... 6 8. analog characteristics (va=vd=3.0v) ................................ ................................ ................................ .... 7 9. filter characteristics (fs=48khz) ................................ ................................ ................................ ............... 8 10. filter characteristics (fs=96khz) ................................ ................................ ................................ ........... 9 11. dc characteristics ................................ ................................ ................................ ................................ .. 9 12. switching characteristics ................................ ................................ ................................ ..................... 10 tim ing diagram ................................ ................................ ................................ ................................ ...... 12 13. functional descriptions ................................ ................................ ................................ ........................ 16 system clock ................................ ................................ ................................ ................................ ........... 16 audio interface format ................................ ................................ ................................ ........................... 16 digital high pass filter ................................ ................................ ................................ ........................... 18 power down ................................ ................................ ................................ ................................ ............ 18 system reset ................................ ................................ ................................ ................................ ........... 19 tdm cascade mode ................................ ................................ ................................ ............................... 19 14. r ecommended external circuits ................................ ................................ ................................ .......... 21 15. package ................................ ................................ ................................ ................................ ................. 23 outline dimensi ons ................................ ................................ ................................ ................................ . 23 material & lead finish ................................ ................................ ................................ ........................... 23 marking ................................ ................................ ................................ ................................ ................... 24 16. revision history ................................ ................................ ................................ ................................ ... 24 important notice ................................ ................................ ................................ ................................ 25
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 3 - 4. pin configurations and functions ordering guide ak5720 ? 4 0 ? +10 5 ? c 16 - pin tssop (0.65mm pitch) akd5720 evaluation board for ak5720 pin layout 1 vcom rin vss lin va vd g sel rego top view 2 3 4 5 6 7 8 c ks fsel b i ck mclk lrck sdto 16 15 14 13 12 11 10 9 dif /tdmi pdn
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 4 - functions no. pin name i/ o function power down status 1 vcom o adc common voltage output pin pull - down to vss with nmos (0.5k 2 s hi - z tdm data input pin hi - z 15 fsel i digital filte r select pin h or l when the pdn pin = h to avoid starting the test mode. handling of unused pin unused i/o pins must be connected appropriately. classification pin name setting analog rin, lin this pin should be open .
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 5 - 5. a bsolute maximum ratings ( vss = 0v ; note 1 ) parameter symbol min max unit power supplies: analog digital va vd ? ? ? vina ? ? ? ? ? ? 6. recommended operating conditions ( vss =0v ; note 1 ) pa rameter symbol min typ max unit power supplies analog (va pin) digital (vd pin) va vd 2.7 2.7 3 or 5 3 or 5 5.5 va v v note 1 . all voltages with respect to ground. warning : akm assumes no responsibility for the usage beyond t he conditions in this datasheet.
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 6 - 7. a nalog characteristics (va=vd=5.0v) ( ta=25 ? c ; va= vd = 5 .0 v; fs=4 8k hz , 96khz ; bick =64fs; s ignal frequency =1khz ; 24bit data; measurement frequency=20hz ? 20khz at fs=48khz, 40hz ? 40khz at fs=96khz; unless otherwise specif ied ) parameter min typ max unit adc analog input characteristics: resolution 24 bits input voltage ( note 2 ) gain = 0db 2. 7 3.0 3.3 vpp gain = +15db 0.48 0.53 0.58 s/(n+d) ( - 1.0dbfs) va=5v gain = 0db fs =48khz, fs=96khz 84 - 94 92 db db va=5v gain = +15db fs=48khz fs=96khz 74 - 84 80 db db dr ( - 60dbfs ) va=5v gain = 0db fs=48khz, a - weighted fs=96khz 94 - 102 99 db db va=5v gain = +15db fs=48khz, a - weighted fs=96khz 83 - 91 86 db db s/n va=5v gain = 0db fs=48khz, a - weighted fs=96khz 94 - 102 99 db db va=5v gain = +15db fs=48khz, a - weighted fs=96khz 83 - 91 86 db db input resistance gain = 0db fs=48khz fs=96khz 29 - 41 28 k ? ? ? ? ? power supplies power supply current normal operation ( pdn pin = ?
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 7 - 8. analog characteristics (va=vd=3.0v) ( ta=25 ? c ; va= vd = 5 .0 v; fs=4 8k hz , 96khz; bick = 64fs; signal frequency =1khz ; 24bit data; measurement frequency=20hz ? 20khz at fs=48khz, 40hz ? 40khz at fs=96khz; unless otherwise specified) parameter min typ max unit adc analog input characteristics: resolution 24 bits input voltage ( note 2 ) gain = 0db 1.65 1.8 1.95 vpp gain = +15db 0.29 0.32 0.35 s/(n+d) ( ? ? ? ? ? ? ? power supplies power supply current normal operation ( pdn pin = ?
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 8 - 9. fil ter characteristics (fs=48khz) ( ta= 25 q c ; va = vd=2.7 a 5.5v, fs=4 8k hz ) parameter symbol min typ max unit adc digital filter (decimation lpf): sharp roll - off ( fsel pin 3 l ) passband ( note 5 ) 0.16 db pb 0 - 18.8 kh z 0. 28 db - 20.0 - khz 3.0 db - 22.8 - khz stopband ( note 5 ) sb 28.4 - - khz stopband attenuation sa 71 - - db group delay distortion 0 ~ 20.0khz ' gd - 0 - 1/fs group delay ( note 6 ) gd - 15.5 - 1/fs adc digital filter (decimation lpf): short delay sharp roll - off filter ( fsel pin 3 h ) passband ( note 5 ) 0.16 db pb 0 - 18.8 khz 0. 28 db - 20.0 - khz 3.0 db - 22.8 - khz stopband ( note 5 ) sb 28.4 - khz stopband attenuation sa 72 - db group delay distortion 0 ~ 20.0khz ' gd - - 2.4 1/fs group delay ( note 6 ) gd - 5.5 - 1/fs adc digital filter (hpf ): frequency response 3.0db fr - 1.0 - hz 0.5db - 2.5 - hz ( note 5 ) 0.1db - 6.5 - hz note 5 . the passband and stopband frequencies scale with fs. for example, pb=0.45 fs(@ 0.1db). note 6 . the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the output register.
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 9 - 10. filter characteristics (fs=96khz) ( ta= 25 q c; va =vd = 2.7 a 5.5v; fs=96khz ) parameter symbol min typ max unit adc digital filter (decimation lpf): sharp roll - off ( fsel pin 3 l ) passband ( note 5 ) 0.16 db pb 0 - 37.6 khz 0. 28 db - 40.0 - khz 3.0 db - 45.6 - kh z stopband ( note 5 ) sb 56.8 - - khz stopband attenuation sa 71 - - db group delay distortion 0 ~ 20.0khz ' gd - 0 - 1/fs group delay ( note 6 ) gd - 15.5 - 1/fs adc di gital filter (decimation lpf): short delay sharp roll - off filter ( fsel pin 3 h ) passband ( note 5 ) 0.16 db pb 0 - 37.6 khz 0. 28 db - 40.0 - khz 3.0 db - 45.6 - khz stopband ( note 5 ) sb 56.8 - khz stopband attenuation sa 72 - db group delay distortion 0 ~ 20.0khz ' gd - - 2.4 1/fs group delay ( note 6 ) gd - 5.5 - 1/fs adc digital filter (hpf): frequency response 3.0db fr - 2.0 - hz 0.5 db - 5.0 - hz ( note 5 ) 0.1db - 13.0 - hz note 5 . the passband and stopband frequencies scale with fs. for example, pb=0.45 fs(@ 0.1db). note 6 . the calculated delay time induced by digital filtering. this time is from the input of an analog signal to the setting of 24bit data both channels to the output register. 11. dc characteristics ( ta= 25 q c , va =vd = 2.7 a 5.5v) parameter symbol min typ max unit high - leve l input voltage low - level input voltage vih vil 7 5 %vd - - - - 25 %vd v v high - level output voltage (iout= 80 p a ) low - level output voltage ( iout= 80 p a ) voh vol vd 0. 4 - - - - 0. 4 v v input leakage current iin - - r 10 p a
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 10 - 12. s witching characteristi cs ( ta= ? 4 0 ? c ? 10 5 ? c ; va = vd=2.7 ? 5.5v; c l =2 0pf , unless otherwise specified ) parameter symbol min t yp max unit master clock timing master clock 256fs: pulse width low pulse width high 384fs: pulse width low pulse width high 512fs: pulse width low pulse width high 768fs: pulse width low pulse width high fclk tclkl tclkh fcl k tclkl tclkh fclk tclkl tclkh fclk tclkl tclkh 2.048 16 16 3.072 11 11 4.096 16 16 6.144 11 11 12.288 18.432 24.576 36.864 24.576 36.864 24.576 36.864 mhz ns ns mhz ns ns mhz ns ns mhz ns ns lrck timing (slave mode) normal mode lrck frequency duty cycle fs duty 8 45 96 55 khz % tdm256 mode lrck frequency lrck timing (master mode) normal mode lrck frequency duty cycle fs duty 8 50 96 khz % tdm256 mode lrck frequency l ti me in i 2 s format.
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 11 - parameter symbol min typ max unit audio interface timing (slave mode) normal mode bick period bick pulse width low pulse width high lrck edge to bick ? ? 2 s mode ) bick ? tbck tbckl tbckh tlrb tblr tlrs tbsd 160 65 65 30 30 35 35 ns ns ns ns ns ns ns tdm256 mode bick per iod bick pulse width low pulse width high lrck edge to bick ? ? ? ? audio interface timing (master mode) normal mode bick frequency bick duty bick ? ? fbck dbck tmblr tbsd ? ? tdm256 mode bick frequency bick duty ( note 9 ) bick ? ? ? fbck dbck tmblr tbss tbsh tsdh tsds ? power - down & reset timing pdn pulse width ( note 10 ) pdn reject pulse width ( note 10 ) pdn ? tpd trpd tpdv 150 4129 30 n s ns 1/fs note 8 . bick rising edge must not occur at the same time as lrck edge. note 9 . in the case of mclk duty cycle is 50% . note 10 . the ak5720 can be reset by setting the pdn pin to l upon power - up. the pdn pin must held l for more han 150ns for a certain reset. the ak 5720 is not reset by the l pulse less than 3 0ns. note 11 . this is the count of lrck f rom the pd n pin = h .
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 12 - timing diagram figure 1 . clock timin g (slave mode) figure 2 . clock timing (master mode) 1/fclk tclkl vih tclkh m c lk vil 1/fs lrck vih vil tlrl tlrh tbck tbckl vih tbckh bick vil 1/fclk tclkl vih tclkh m clk vil 1/fs lrck 50% v d t lrh 1/fbck tdbckl tdbckh bick 5 0% v d db ck = t d bckh (or t d b ckl) x fs x 100
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 13 - figure 3 . audio interface timing ( normal mode & slave mode) figure 4 . audio interface timing ( tdm mode & slave mode) tlrb lrck vih bick vil tlrs sdto 5 0% vd tbsd vih vil tblr tlrb lrck vih bick vil sdto 5 0% vd tbss vih vil tblr tsds t d m i vih vil tsdh tbsh
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 14 - figure 5 . audio interface timing ( normal mode & master mode) figure 6 . audio interface timing ( tdm mode & master mode) lrck bick sdto tbsd tmblr 50% v d 50% v d 5 0% v d lrck bick sdto tbsh tmblr 5 0% v d 5 0% v d 5 0% v d t d m i tsdh tsds vih vil tbss
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 15 - figure 7 . po wer - down & reset timing vih vi l 50%v d tpd sdt o pd n tpd v trp d
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 16 - 13. functional descriptions v system clock mclk, b ic k and lrck (fs) clocks are required in slave mode. the lrck clock input must be synchronized with mclk, however the phase is not critical. table 1 shows the relationship of typical sampling frequency and the system clock frequency. all external clocks (mclk, b ic k and lrck) must be present unless pdn pin = 3 l . if the external clocks a re not present, place the ak5720 in power - down mode (pdn p in = 3 l ). in master mode, the master clock (mclk) must be provided unless pdn pin = 3 l . fs mclk 128fs 192fs 256fs 384fs 512fs 768fs 32khz n/a n/a 8.192mhz 12.288mhz 16.384mhz 24.576mhz 44.1khz n/a n/a 11.2896mhz 16.9344mhz 22.5792mhz 33.8688mhz 48k hz n/a n/a 12.288mhz 18.432mhz 24.576mhz 36.864mhz 96khz n/a n/a 24.576mhz 36.864mhz n/a n/a table 1 . system clock example v audio interface format mclk frequency, the relationship of bic k frequency and fs, and master/slave mod e are set by external res ista nce value of the cks pin and the cks pin connection as shown in table 2 . when the cks pin is connected to gnd or va directly, or via an external 4.7k resistor ( n ormal m ode ) , the dif/tdmi pin becomes a n audio data format select pin. two kinds of data formats : 24bit msb justified an d i 2 s formats can be chosen by the dif pin . the audio data is outpu t on the falling edge of bick from the sdto pin . the audio interface supports both master a nd slave modes. i n master mode, bic k and lrck are output and they are input in slave mode. in master mode, lrck frequency is fixed to 1fs and the bick frequency is fixed to 64 fs. when the cks pin is connected to gnd or the va pin via an external resistor of 18k or 82k (tdm mode), the dif/tdmi pin becomes a tdm data input pin. in tdm mode, the audio data is output on a rising edge of bick from the sdto pin. when inputting the sdto output data to the tdmi pin, this sdto data has a delay which fills set - up or hol d time of bick rising . mode cks dif /tdmi sdto master /slave mclk lrck bick 0 normal < 10 wr*1' (short to gnd) l msb slave 256/384fs (8k d fs d 96k) 512/768fs (8k d fs d 48k) h/l t 48fs or 32fs 1 h i 2 s l/h 2 < 10 wr va (short to va) l msb master 256 fs (8k d fs d 96k) h/l 64fs 3 h i 2 s l/h 4 4.7 n ? 10 % to gnd l msb master 384fs (8k d fs d 96k) h/l 64fs 5 h i 2 s l/h 6 4.7 n ? 10 % to va l msb master 512fs (8k d fs d 48k) h/l 64fs 7 h i 2 s l/h 8 tdm 18 n ? 10 % to gnd tdmi msb master 256fs (8k d fs d 96k) n 256fs 9 18 n ? 10 % to v a tdmi msb slave 256fs (8k d fs d 96k) n 256fs 10 82 n ? 10 % to gnd tdmi i 2 s master 256fs (8k d fs d 96k) p 256fs 11 82 n ? 10 % to v a tdmi i 2 s slave 256fs (8k d fs d 96k) p 256fs table 2 . operation mode select note 12 . sdto outputs 16 - bit data when bic k=32fs.
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 17 - figure 8 . mode 0, 2, 4, 6 timing (normal mode, msb justified) figure 9 . mode 1, 3, 5, 7 timing (normal mode, i 2 s compatible) figure 10 . mode 8 , 9 t iming (tdm256 mode, msb justified) figure 11 . mode 1 0 , 11 timin g (tdm256 mode, i 2 s compatible) lrck bick(64fs) sdto 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 lch data rch data 12 11 10 23:msb, 0:lsb lrck bick(64fs) sdto 0 1 2 3 23 24 25 26 0 0 1 31 29 30 23 22 1 23:msb, 0:lsb lch data rch data 2 0 2 3 23 24 25 26 0 31 29 30 23 22 1 2 0 1 23 lrck (mode 9 ) bick (256fs) sdto 22 0 l 32 bick 256 bick 22 0 r 32 bick 22 23 23 lrck (mode 8 ) lrck (mode 11 ) 5) bick (256fs) sdto 23 0 l 32 bick 256 bick 23 0 r 32 bick 23 lrck ( mode 10 )
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 18 - digital high pass filter the adc has a digital high pass filter for dc offset cancellation. the cut - off frequency of the hpf is 1.0hz (@fs=48khz) and scales with sampling rate (fs). power d own the ak 5720 is placed in the power - down mode by bringing the pdn pin to l . t he digital filter is also reset at the same time. this reset should always be executed upon power - up. in power - down mode, vcom becomes vss level. the ak5720 will be in an alog initialization cycle after exiting the powe r - down mode. therefore, the sdto output data becomes valid after 4129 cycles of lrck clock in master mode or 4132 cycles of lrck clock in slave mode when power up the ak5720 . during initialization , both l and r channels of adc digit al data outputs are forc ed to 0 in 2 s complement. the adc outputs settle as a data co rresponding to the input signals after the end of initialization ( this s ettling takes approximately group delay time). figure 12 . power - do wn/up timing example notes: (1) the pdn pin must be l when power up the ak 5720 and set to h after all poweres are supplied. (2) the internal power - down state is released after 147456/ mclk cycles. (3) there is a delay about 3~4fs from internal power - up to the start of initialization cycle. (4) digital block of the adc is initialized after internal power - down is released. when start - up the ak 5720 , adc input voltage should be operat ion common voltage. a charge - up time of dc cut capacitor is necessary t o wait until the rin and lin pins settle to the common voltage . when the external capacitor is 1 0 f , the status of these pin settles in = 400m s ( typ ). (5) click noise occurs at the end of initialization in the digital part. mute the adc output ex ternally if the click noise influences system applications. (6) digital output corresponds to analog input ha s group delay (gd). (7) adc output s 0 data in power - down state. adc internal state internal pdn clock in mclk,lrck, bick adc in (analog) adc out (digital) rego power - down don t care gd 0 data (6 ) (7 ) 4129 /fs init cycle normal operation (4 ) gd ( 5 ) 0 data don t care (1 ) vcom pdn va/vd ( 2 ) 3~4/fs ( 3 )
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 19 - system reset the ak5 720 should be reset once by bringing the pdn pin to l after power - up. in slave mode, reset and power - down are released on the rising edge (falling edge in i 2 c compatible mode ) of lrck after setting the pdn pin = h . in master mode, reset and power - down are released by mclk input after setting the pdn pin = h . tdm cascade mode tdm256mode four or less devices can be connected in cascades at the tdm 256 mode. in figure 13 , the sdto pin of device #1 /#2/# 3 is connected with the tdmi pin of device #2 /#3/# 4. it is possible to output 8 channel tdm data from the sdto pin of device #4 as shown in figure 14 . figure 13 . cascade tdm connection diagram 48kh z 256 fs 8 ch tdm 256fs gnd lrck ak572 0 #1 bick dif/ tdmi sdto mclk lrck ak57 2 0 #2 bick dif/ tdmi sdto mclk lrck ak572 0 #3 bick dif/ tdmi sdto mclk lrck ak572 0 #4 bick dif/ tdmi sdto mclk
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 20 - figure 14 . cascade tdm timing (tdm256 mode (left justified)) lrc k (slave) bick(256fs) #1 sdto (o) 22 0 l - #1 32 bick 256 bick 22 0 r - #1 32 bick 22 23 23 23 #4 tdmin(i) 22 0 l - #3 32 bick 22 0 r - #3 32 bick 23 23 22 0 l - #2 32 bick 22 0 r - #2 32 bick 23 23 #4 sdto (o) 22 0 l - #4 32 bick 22 0 r - #4 32 bick 22 23 23 23 22 0 l - #3 32 bick 22 0 r - #3 32 bick 23 23 22 0 l - #2 32 bick 22 0 r - #2 32 bick 23 23 22 0 l - #1 32 bick 22 0 r - #1 32 bick 23 23 22 0 l - #1 32 bick 22 0 r - #1 32 bick 23 23 lrck (master)
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 21 - 14. r ecommended external circuits figure 15 shows the system connection diagram. an evaluation board (akd5720) is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. note: - a ll digital input pins should not be left floating. figure 15 . typical connection diagram vcom 1 rin 2 lin 3 vss 4 va 5 vd 6 gsel 7 rego 8 16 15 14 13 12 11 10 9 cks fsel pdn bic k mclk lrck sdto ak5720 0.1 ? analog supply 10 ? + controller system ground analog ground dif/tdmi reset + 0.47 ? mode setti ng 2.7 ? 5.5v 0.1 ? 10 ? + digital supply 2.7 ? 5.5v 10 ? 10 ? + 1 ?
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 22 - 1. grounding and power supply decoupling the ak 5720 requires careful attention to power supply and grounding arrangements. alternatively i f va and vd are supplied separately, the power up sequence is not critical. vss of the ak5720 must be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the pri nted circuit board. decoupling capacitors should b e as near to the ak5720 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference the voltage input to va set s the analog input range. vcom is 50%va and used as the common voltage of analog signal s . the vcom pin is connected to vss . a 0.47 ? f ceramic capacitor should be connected as close to the vcom pin as possible between vss and the vcom pin . no load current may be drawn from these pins. all signa ls, esp ecially clocks, should be kept away from the vcom pin in order to avoid u nwanted coupling into the ak5720 . 3. analog inputs the adc inputs are single - ended and internally biased to the common voltage (50%va) with 41 k ? (typ@fs=48khz) resistance. the input signal range scales with the suppl y voltage and nominally 0.6 va vpp (typ). the adc output data format is 2 s complement. the internal hpf removes the dc offs et ( includes the dc offset that is caused by the adc ) . the ak 5720 samples the analog inputs at 6 4fs. the digital filter rejects noise above the stop band except for multiples of 64fs. the ak5720 includes an anti - aliasing filter (rc filter) to attenuate a noise around 64fs. 4. external re sistor of the c k s pin the external resistor of the c k s pin sho uld be close as possible to the pin and kept away from the signal lines to prevent noises in to the c k s pin.
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 23 - 15. package outline dimensions material & lead f inish package molding compound: epoxy lead frame mater ial: cu lead frame surface treatment: solder (pb free) plate 0 -10 ? detail a seating plane 0.10 0.17 ? 0. 0 5 0. 22 ? 0.1 0.65 *5.0 ? 0.1 1.05 ? 0.05 a 1 8 9 16 16 pin tssop (unit: mm) *4.4 ? 0.1 6.4 ? 0.2 0.5 ? 0.2 0.1 ? 0.1 note: dimension "*" does not include mold flash. 0.13 m
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 24 - marking 1) pin #1 indication 2) date code : xx x yy ( 5 digits) xx x : week code yy : factory co ntrol code 3) marketing code : 5720 vt 4) asahi kasei logo 16. revision his tory date (y/m/ d) revision reason page contents 14 / 04/ 17 00 first edition 14/10/1 7 01 error correction 22 3. analog inputs the ak5720 samples the analog inputs at 64fs(@fs=48khz). ? ? ? ? akm 5720 v t xx x yy
[ ak5 720 ] m s1641 - e - 0 2 2014/1 2 - 25 - important notice 0. asahi kasei microdevices corporation (akm) reserves the right to m ake changes to the information contained in this document without notice. when you consider any use or application of akm product stipulated in this document ( product ) , please make inquiries the sales office of akm or authorized distributor s as to curren t status of the products. 1. all information included in this document are provided only to illustrate the operation and application examples of akm products . akm neither makes warranties or representations with respect to the accuracy or completeness of t he information contained in this document nor grants any license to any intellectual property rights or any other rights of akm or any third party with respect to the information in this document. you are fully responsible for use of such information conta ined in this document in your product design or applications . akm assumes no liability for any losses incurred by you or third parties arising from the use of such information in your product design or applications. 2. the product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage or serious public impact , includi ng but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment, equipment used to control combust ions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. do not use product for the above use unless specifically agreed by akm in writing . 3. though akm works continuall y to improve the products quality and reliability, you are responsible for complying with safety standards and for providing adequate designs and safeguards for your hardware, software and systems which minimize risk and avoid situations in which a malfun ction or failure of the product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. 4. do not use or otherwise make available the product or related technology or any information contained in this documen t for any military purposes, including without limitation, for the design, development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons). when exporting the p roducts or related technology or any information contained in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. the p roducts and related technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 5. please contact akm sales representative for details as to environmental matters such as the roh s compatibility of the product. please use the product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. akm assumes no liability for dam ages or losses occurring as a result of noncompliance with applicable laws and regulations. 6. resale of the product with provisions different from the statement and/or technical features set forth in this document shall immediately void any warranty granted by akm for the product and shall not create or extend in any manner whatsoever , any liability of akm. 7. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of akm .

▲Up To Search▲

Price & Availability of AK5720VT

	To Download AK5720VT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .